Design Verification Engineer

Summary : Seeking an FPGA Design Verification Engineer to define verification methodology and create scalable simulation environments for complex FPGAs.

Requirements :

• Bachelor's degree in Electrical or Computer Engineering, or related field
• Minimum of 8 years relevant experience (6 years with a Master's degree)
• Experience defining verification methodology for complex FPGAs
• Ability to analyze requirements and create test plans
• Skilled in building and setting up simulation environments using SystemVerilog / UVM

Preferred Skills :

Responsibilities :

Equal Opportunity Employer / Veterans / Disabled

Benefit offerings include medical, dental, vision, term life insurance, short-term disability insurance, additional voluntary benefits, commuter benefits and 401K plan. Our program provides employees the flexibility to choose the type of coverage that meets their individual needs. Available paid leave may include Paid Sick Leave, where required by law; any other paid leave required by Federal, State or local law; and Holiday pay upon meeting eligibility criteria. Disclaimer : These benefit offerings do not apply to client-recruited jobs and jobs which are direct hire to a client

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The Company will consider qualified applicants with arrest and conviction records.