Remote Interior design Jobs in Lancaster, CA

Job Title : Sr Logic Design (RTL) Engineer

Location : Santa Clara, CA

Position Type : Contract

Duration : 6 / 12 Month

Work Type : Remote

Rate : Pay range offered to a successful candidate will be based on several factors, including the candidate's education, work experience, work location, specific job duties, certifications, etc.

Job Description :

The RTL Engineer performs detailed block design from system requirements and evolving specifications.

Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with Synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power, and area goals

Develop HW architecture from specification documents.

Take complete responsibilities include writing RTL code for IP development / RTL integration, checking the code for Lint / CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog / System Verilog / VHDL.

Develop and execute low power design (UPF / CPF).

Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc.

Knowledge of JESD204C block design and related design / verification experience (includes licensed IP & PHY from 3rd parties)

Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.

Carry out static checks including Lint / CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.

Take ownership of tasks and drive tasks to closure.

Requirements :

Bachelor's or master's in electrical or computer engineering or related field

12+ years of experience in Logic (RTL) Design

Preferred Qualifications :

Greteams.

Experience with advanced peripheral bus IP's such as GPIO, UART, SPI, SW, JTAG, and I2C.

Strong fundamentals in VLSI design, and Digital Design Architecture

Strong problem-solving and data analysis skills

Strong skills using scripting languages such as Perl, TCL, Python.

Excellent interpersonal skills and able to work with remote teams

Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.

Knowledge of low-speed bus protocols (AMBA / OCP) and high-speed serial protocols (PCIe / USB / Ethernet) will used at various stages of the design Key Responsibilities-Develop HW architecture from specification documents.

Take complete responsibilities include writing RTL code for IP development / RTL integration, checking the code for Lint / CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog / System Verilog / VHDL.

Develop and execute low power design (UPF / CPF).

Design top level RTL, integration of blocks, clocks, resets, configuration registers, at communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive etc

Develop HW architecture from specification documents.

Take complete responsibilities include writing RTL code for IP development / RTL integration, checking the code for Lint / CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog / System Verilog / VHDL.

Develop and execute low power design (UPF / CPF).

Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc.

Knowledge of JESD204C block design and related design / verification experience (includes licensed IP & PHY from 3rd parties)

Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.

Carry out static checks including Lint / CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.

Take ownership of tasks and drive tasks to closure.

Synopsys or Cadence RTL Compilers (Priority : 1)

Debussy (Priority : 1)

Python (Priority : 3)

Synopsys or Cadence EDA Tools (Priority : 1)