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Descripción del trabajoUnderstand Submodule Functionality : Comprehend the submodule functionality and requirements through design specifications provided by the architecture owner. Work with upper-level design integrators to identify sub-module interface protocols. Create quality digital designs using System Verilog RTL that meets the computational functions or control sequences specified in the design specifications, and perform basic module-level verification using the provided SW-based verification environment. Perform RTL Sign-Off Checks : Conduct RTL sign-off checks, including LINT, CDC, CLP, and RDC verification. Supply necessary collateral for physical design, including SDC / UPF, and collaborate with the physical design team to perform performance-critical path analysis of the assigned design block. Validate Design Functionality : Work with the design verification team to ensure the design's functionality. Educational Background : students currently enrolled in a master's degree program in computer engineering, electrical engineering, or an equivalent field. Relevant Coursework : Completed coursework in VLSI Design or Integrated Circuits, Computer Architecture, Digital Logic Design, and Design for Testing. RTL Knowledge : Proficiency in System Verilog coding is preferred. Communication and Teamwork : Strong communication, presentation, and teamwork skills. Programming Languages : Knowledge of scripting languages such as Tcl, Perl, and Python is a plus.
About the Company - MediaTek is the world’s fifth largest fabless IC design company, offering a diverse range of products for AI, smartphones, smartwatches, tablets, WiFi, TV, Automotive, data center processing and interconnect, voice assistant devices, drones, navigation systems and so on, most of which have the biggest market share in the world. At MediaTek, we foster a diverse and supportive culture that empowers employees to achieve their ultimate potential. We are ranked second in Newsweek's 2024 list of the World's Most Trustworthy Companies for Technology Hardware and one of Forbes’ World’s Best Employers 2024.
About the Role - We are seeking motivated students interested in RTL development for mixed-signal design to join our Summer 2025 Internship Program. As an RTL Design Intern, you will gain the experience of collaborating closely with both digital and analog designers to understand high-level mixed-signal system operations; develop digital designs using System Verilog RTL and conduct design quality verification checks. You will be assigned to a submodule of the mixed-signal power and performance management system used in high-performance CPU system. This role offers hands-on experience in :
- Balancing circuit performance with data process latency, design area, and computation accuracy.
- Design quality check methodology and flow using Industry standard EDA tools.
- SW-sequence-based mixed-signal design verification flow.
Responsibilities
Qualifications
Equal Opportunity Statement
MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.